Business Wire

Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...
EDN

Aldec tools validated for Lattice devices

SAN FRANCISCO — Mixed-language simulation and EDA tool provider Aldec Inc. said Monday (May 15) that programmable logic supplier Lattice Semiconductor Corp. has validated Aldec's Riviera and ...
Design-Reuse

Aldec and Actel Deliver Co-verification Solution for ARM-based FPGA Design

HENDERSON, Nev. & MOUNTAIN VIEW, Calif.--March 12, 2007--Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, today announced the release of ...
Electronic Design

EDA Update: Mixed HDL/C-Language Design For FPGAs

Mixed HDL/C-Language design for FPGAs recently debuted, courtesy of Aldec Inc. and Celoxica Ltd. The Active-HDL+C integrated FPGA design environment combines Aldec's Active-HDL design entry and ...
EDN

Co-verification tool targets FPGA processors

SANTA CRUZ, Calif. — Making its entry into the embedded systems market, Aldec Corp. this week (Sept. 15) is announcing CoVer, a hardware/software co-verification tool aimed at FPGA designers. The tool ...
Electronic Design

Graphical Code Coverage Tool Speeds Design Debugging

Code Snooper, a code coverage software tool for use with the Active-HDL design and verification environment is integrated with the Active-HDL simulation kernel and does not require additional ...