Microchip has developed a single-I/O bus UNI/O EEPROM devices in miniature, wafer-level chip-scale and TO-92 packages, in addition to the 3-pin SOT-23 package. Measuring 0.85 mm x 1.38 mm, the ...

Wafer-scale technology is making waves again, this time promising to enable artificial intelligence (AI) models with trillions of parameters to run faster and more efficiently than traditional ...

If you thought a chip like AMD's MI300A was big at 146 billion transistors, you ain't seen nothing yet. AI company Cerebras announced its third-generation AI chip, CS-3, a "wafer-scale" silicon ...

Over the past year, companies like Cerebras have made headlines for their use of wafer-scale processing. TSMC wants to grow this area of its business and plans to build out its InFO_SoW (Integrated ...

With the introduction of its first wafer level chip scale packaged Schottky, Diodes Incorporated is providing smartphone and tablet designs with an alternative to miniature DFN0603 devices that offers ...

At the end of January, Advanced Chip Engineering Technology (ACE) will begin applying its WLCSP (wafer-level chip-scale package) burn-in, packaging and testing solution to 256Mbit DDR (double data ...

A panel-level (PL) approach to fan-out (FO) packaging has been discussed for several years to reduce the cost of chip-first FO packaging based on redistribution layer (RDL) technology. More recently, ...