EDN

In-design metal fill key to physical verification turnaround time for advanced IC designs

Escalating design size and complexity, more complex design-rule checks (DRCs), higher DRC rule count and increasing design-for-manufacturability (DFM) challenges are causing the physical verification ...
EDN

Chip Design Verification: It’s All About the Coverage

As the cost of chip turns has grown from thousands to millions of dollars, missed design bugs are unacceptable Chip design verification used to be straightforward, if not always easy. Verification ...
Design-Reuse

Advanced Techniques for IP Design and Verification

As designs grow in size and complexity, the challenges associated with low power and the growing design and verification gap have created the need for a paradigm shift in the IP design and ...
Design-Reuse

Improving ASIC Design Verification using FPGAs and Structured ASICs

Structured ASICs require developers to re-program only the top level metal layers when customizing their designs, enabling faster development time and low unit cost. However, many structured ASICs ...
Electronic Design

Transaction-based Verification And Emulation Combine For Multi-megahertz Verification Performance

This file type includes high resolution graphics and schematics. Design complexity has grown with each successive generation of system-on-chip (SoC) evolution. SoCs now include many industry-standard ...
Electronic Design

11 Myths About Verification IP

It’s time to put to rest 11 of the most common myths about verification intellectual property (VIP). SmartDV’s Bipul Talukdar, Director of Applications Engineering, explains why it’s used in a ...