Three years ago, I wrote a blog entitled “Linking Virtual Wafer Fabrication Modeling with Device-level TCAD Simulation,” in which I described the seamless connection between the SEMulator3D virtual ...

To address emerging custom circuit design challenges, Mountain View, Calif.-based EDA giant Synopsys Inc. today unveiled its anticipated next-generation transistor-level static timing analysis tool, ...

Almost every chip being taped out today is mixed-signal in nature. In addition to increased integration of analog and RF blocks, designers are using complex power-management techniques to minimize ...

Efficiency is the name of the game in power-system design, driven by the need to better leverage available energy and deliver more power from a smaller package. Except in some specialized or extremely ...

About 15 years ago, the assumption in the EDA industry was that system design would be inevitable. The transition from gate-level design to a new entry point at the register transfer level (RTL) ...

WEST LAFAYETTE, Ind. — A hacker can reproduce a circuit on a chip by discovering what key transistors are doing in a circuit – but not if the transistor “type” is undetectable. Purdue University ...

A team of scientists from the Institute for Basic Science has developed a revolutionary technique for producing 1D metallic materials with a width of less than 1 nm by epitaxial growth. Using this ...

A review paper by scientists at Beijing Institute of Graphic Communication presented  a thorough review of the existing ...

IBM announced last week that it has developed the technology to produce chips with 2nm transistors. You may remember from other episodes of our explainer show, Upscaled, that smaller transistors ...