September 30, 2014. Keysight Technologies today introduced the DDR Bus Simulator—the industry’s first tool to generate accurate Bit-Error-Rate (BER) contours for the JEDEC DDR memory bus specification ...
DDR verification is one of the most critical and complex tasks in any SoC as it involves a controller sitting inside the DUT and an external DDR memory sitting outside the DUT on board. A DDR system ...
No matter how advanced Static Timing Analysis (STA) tools become, there are still a lot of advantages to running GLS, since it has the capability of uncovering a lot of hidden design issues which are ...
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