EDN

Two gates and a microprocessor form digital PLL

You can use Microchip's low-cost PIC16F818 microprocessor and a pair of gates to construct a digital PLL that can clean noisy digital signals over a range of 4 to 40 kHz. Featuring programmable lock ...
Design-Reuse

PLL Lock detector with low current consumption and high accuracy

The lock detector monitors the current status of PLL by comparing the phase difference of VCO divided signal and reference oscillator signal with requ ...
Electronic Design

Detector Identifies PLL State

Suitable for synchronization of optical networking equipment, PLLs, synthesizers, and other telecom applications, the Model SY13 frequency and phase-lock detector compares two external input signals ...
Electronics Weekly

Analogue or digital in PLL design

The performance of analogue phase-locked loops (PLLs) has steadily improved with operating frequencies extending to 8GHz and beyond. Recently, digital PLLs based on direct digital synthesis (DDS) have ...
Design-Reuse

Achieving Groundbreaking Performance with a Digital PLL

Digital PLLs outperform analog PLLs in jitter, phase noise, power, and die area. They also reduce migration risk and cost. They make integration and production test easy. Yet, they have not been ...
EDN

Tracking PLL design through the decades, part 2

The desire to integrate more gateshas driven two advances in CMOS-processingtechnology, enabling the integrationof practical inductors in genericCMOS-logic processes. The first, theuse of CMP ...