Semiconductor Engineering

How Die Dimensions Challenge Assembly Processes

Multi-die assemblies are becoming more common and more complex due to technology advancements and market demands, but differing die dimensions are making this process increasingly challenging. To ...
Semiconductor Engineering

Challenges Grow For Creating Smaller Bumps For Flip Chips

New bump structures are being developed to enable higher interconnect densities in flip-chip packaging, but they are complex, expensive, and increasingly difficult to manufacture. For products with ...
Seeking Alpha

Onto Innovation Advances Process Control Suite for 3D Interconnect Yields

WILMINGTON, Mass.--(BUSINESS WIRE)-- Onto Innovation Inc. (ONTO) today announced advances in its product suite for 3D interconnect process control, featuring the new 3Di ™ technology on the Dragonfly ...
EDN

Xilinx uses Unitive’s eutectic wafer-bumping process to lower FPGA costs

RESEARCH TRIANGLE PARK, N.C. — Flip-chip technology supplier Unitive Inc. here today announced qualification of its eutectic wafer-bumping process for volume production of high-density ...
EDN

Solder-bump technology breaks cooling, power-generation constraints

A potential breakthrough technology from Nextreme (Research Triangle Park, NC)—a microscale thermal and power-management device manufacturer—integrates cooling and power-generation capabilities into ...