Semiconductor Engineering

Improving Test Coverage And Eliminating Test Escapes Using Analog Defect Analysis

While the analog and mixed-signal components are the leading source of test escapes that result in field failures, the lack of tools to analyze the test coverage during design has made it difficult ...
Business Wire

Cadence Debuts Industry’s First Analog IC Design-for-Reliability Solution

MUNICH--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ: CDNS) today introduced the Cadence ® Legato™ Reliability Solution, the industry’s first software product that meets the challenges of ...
EDN

Test methods identify small delay defects

Today's systematic and more subtle random defects are not only decreasing yields, but are also increasing the number of test escapes, or defective parts per million (DPPM) shipped out. One of the ...
Nature

Magnetic Flux Leakage Testing and Defect Detection

Magnetic flux leakage (MFL) testing is a widely established non‐destructive evaluation technique used to assess the integrity of ferromagnetic materials in applications such as pipeline inspection and ...
EDN

Test’s role on the path to zero-defect devices

Read more about meeting the individual challenges of digital zero-defect testing and details of approaches to dealing with these challenges. The effectiveness of semiconductor manufacturing test has a ...
Electronic Design

Understanding Cell-Aware ATPG And User-Defined Fault Models

ATPG targets faults at IC-gate boundaries, but 50% of defects are located within cells. Learn how cell-aware ATPG and user-defined fault models help to ferret out these hard-to-squash bugs.