Semiconductor Engineering

Freeing Up Near-Memory Capacity For Cache Using Compression Techniques In A Flat Hybrid-Memory Architecture

A technical paper titled “HMComp: Extending Near-Memory Capacity using Compression in Hybrid Memory” was published by researchers at Chalmers University of Technology and ZeroPoint Technologies.
Nature

Cache Management and Partitioning in Multicore Systems

Modern multicore systems demand sophisticated strategies to manage shared cache resources. As multiple cores execute diverse workloads concurrently, cache interference can lead to significant ...
Semiconductor Engineering

An Energy-Efficient DRAM Cache Architecture for Mobile Platforms With PCM-Based Main Memory

“A long battery life is a first-class design objective for mobile devices, and main memory accounts for a major portion of total energy consumption. Moreover, the energy consumption from memory is ...
Electronic Design

Adding Cache to IPs and SoCs

Cache memory significantly reduces time and power consumption for memory access in systems-on-chip. Technologies like AMBA protocols facilitate cache coherence and efficient data management across CPU ...
Gizmochina

Snapdragon 8 Gen 4 utilizes a new GPU architecture with improved cache and memory compression tech, claims tipster

Qualcomm‘s next flagship mobile processor, the Snapdragon 8 Gen 4, is expected to launch later this year, and rumors regarding its features are picking up steam. A new leak by Weibo tipster Digital ...
CSOonline

New Linux kernel cross-cache attack allows arbitrary memory writes

Researchers from the Graz University of Technology have discovered a way to convert a limited heap vulnerability in the Linux kernel into a malicious memory writes capability to demonstrate novel ...