EDN

CN-0302: Ultra-Fast Settling PLL with RF to 13 GHz block diagram

The PLL circuit shown in Figure 1 uses a 13 GHz Fractional-N synthesizer, wideband active loop filter and VCO, and has a phase settling time of less than 5 μs to within 5° for a 200 MHz frequency jump ...
Design And Reuse

Creating a Frequency Plan for a System using a PLL

Perceptia Devices is an IP and design services provider, based in Sydney, Australia and Silicon Valley. It is focused on PLLs for RF systems and demanding clocking applications. Perceptia offers a ...
EDN

PLL Subsystem architectures for SoC design

Because of the cornerstone importance of PLLs to an SoC design, this article considers the various challenges in the design of PLL subsystems, and discuss architectural solutions. The PLL subsystem is ...