EDN

Using an 8:1 Multiplexer to Implement a 4-input Logical Function

Now, the thing to remember is that we are using a CD4512 chip, whose truth table is shown below. The important thing to note here is that, in addition to the three multiplexer select controls, A, B, ...
TechRepublic

Power Optimization of 8:1 MUX Using Transmission Gate Logic (TGL) with Power Gating Technique

In this paper, the authors aim at reducing power and energy dissipation in Transmission Gate Logic (TGL) multiplexer CMOS circuits comprise of reducing the power supply voltages, power supply current ...
EDN

1-of-8 FET Multiplexer/Demultiplexer

The CBT3251 is a 1-of-8 FET multiplexer/demultiplexer. This high speed device has TTL-compatible input levels. It features 5-ohm switch connection between two ports ...
Electronic Design

D-Type Flip-Flop Synchronizes Multiplexer Data

Multiplexers are widely used in communication systems to convert parallel signals into serial signals. The multiplexer takes a high-frequency clock as the system input clock (Clk_in) that's ...
Design-Reuse

12bit 1MSPS SAR ADC with 8-1 Mux (All C-type) ; UMC 0.13um LL/RVT FSG Logic Process

12bit 1MSPS SAR ADC with 8-1 Mux (All C-type) ; UMC 0.13um LL/RVT FSG Logic Process ...
Design-Reuse

Clock Gating Checks on Multiplexers

With the increasing complexity of design in today’s fast changing world, the thrust on power saving has increased manifold. Consequently, gating the most toggling signal on the SoC i.e. the clock has ...